A superscalar processing system includes multiple execution units for simultaneously executing multiple instructions. In some processing systems, instructions are executable out-of-order relative to their programmed sequence within the instruction stream. Nevertheless, some of these processing systems are designed to dispatch instructions to execution circuitry in-order of the instructions' programmed sequence. According to typical previous techniques, such in-order dispatch adversely impacts the processing system's ability to dispatch multiple instructions during a single machine cycle, particularly as the single machine cycle is shortened.
Thus, a need has arisen for a processing system and method of operation, in which in-order dispatch less adversely impacts the processing system's ability to dispatch multiple instructions during a single machine cycle.